The present invention relates to a digital differential analyzer for resolving a differential equation.
The digital differential analyzer (hereinafter referred to DDA) has been used as a means for resolving the differential equation and it operates based on a principle of calculating an area of segmented regions. The DDA can be classified into a serial type DDA in which a digital integrator performs operations step by step in serial and a parallel type DDA in which all of the digital integrators perform operations simultaneously. The former has advantages of low cost because an arithmetic unit including the integrator can be commonly used and of simple compensating operation and high accuracy of the result because preoperated result of the integrator can be used in the subsequent operations. Therefore, the former has been frequently used in the past. However, it has a disadvantage of low operation speed because the digital integrator performs the operations step by step. On the other hand, the latter allows a high speed operation because all of the digital integrators perform the operations simultaneously. However, since inputs (primary increment and secondary increment) to the digital integrator are always limited to those of one or more iteration times earlier, different compensating operations are required depending on the degree of delay of those inputs. As the compensating operation becomes complex, arithmetic circuits required become complex accordingly. Thus, in the parallel type DDA in which one arithmetic circuit is required for each of the digital integrators, it is difficult to attain a practical DDA unless the arithmetic circuits are constructed by a fewer number of circuit components and the operations are carried out at a high speed. Like in a conventional digital computer, the operation within the DDA can be classified into three categories, that is, a serial addition method in which data are added bit by bit, a parallel addition method in which all bits are added simultaneously and a combination thereof. The serial type DDA in which the common arithmetic unit can be used generally employs the parallel addition method in order to attain a higher operation speed while the parallel type DDA generally employs the serial addition method in order to reduce the number of components. However, since the parallel addition method is superior in the operation speed to the serial addition method, some of the parallel type DDA employ the parallel addition method to attain the high operation speed. In the parallel addition method, matching of bit positions of an integrated result and a secondary increment is necessary in producing a sum thereof and this governs the operation time of the DDA.
The DDA's of the types described above each includes an adder for calculating the integrated value, an adder for performing the compensating operation and an adder for performing quantizing operation to generate a tertiary increment, all of those adders being connected directly in cascade. When an operation is to be carried out in the DDA of the serial addition type, for example, the operations by all of the above adders are carried out for one bit of the data representative of the integrated value and then the operations are repeated for the next bit. In the DDA of the parallel addition type, after the operations for one data have been completed, the operations for the next data are carried out.
Thus, a long operation time has been heretofore been required and this has been blocking the achievement of the high speed operation.
Furthermore, only a relatively simple compensating operation could be performed and hence the parallel type DDA which required a complex compensating operation had a problem in the operation accuracy.